000 00301nam a2200121Ia 4500
008 200701s2003 xx 000 0 eng d
100 _aSUDHAKAR YALAMANCHILLI
245 0 _aINTRODUCTORY VHDL FROM SIMLATION TO SYNTHESIS
250 _a3rd
260 _bPEARSON
_c2003
300 _a401
942 _2ddc
_cGE
999 _c2370
_d2370